View TEA6415CDT_5843751.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

tea6415c bus-controlled video matrix switch ? this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. september 2003 1/11 main features n 20 mhz bandwidth n cascadable with another tea6415c (internal address can be changed by pin 7 voltage) n 8 inputs (cvbs, rgb, chroma, ...) n 6 outputs n possibility of chroma signal for each input by switching off the clamp with an external resistor bridge n bus controlled n 6.5 db gain between any input and output n -55 db crosstalk at 5 mhz n full esd protection description the main function of the tea6415c is to switch 8 video input sources on the 6 outputs. each output can be switched to only one of the inputs, whereas any single input may be connected to several outputs. all switching possibilities are controlled through the i 2 c bus. so 20 (plastic small outline package) order code: tea6415cd dip 20 (plastic dual in-line package order code: tea6415c input ground output output output output output output ground input input data input clock input input prog input vcc input t 1 2 3 4 5 6 7 8 9 10 e a 6 4 1 5 c 20 19 18 17 16 15 14 13 12 11 7
2/11 tea6415c general description 1 general description the main function of the tea6415c is to switch 8 video input sources on the 6 outputs. each output can be switched to only one of the inputs, whereas any single input may be connected to several outputs. the lowest level of each signal is aligned on each input (bottom of sync pulse for cvbs or black level for rgb signals). the nominal gain between any input and output is 6.5 db. for chroma signals, the alignment is switched off by forcing, with an external 5 v dc resistor bridge on the input. each input can be used as a normal input or as a chroma input (with external resistor bridge). all the switching possibilities are changed through the i2c bus. driving a 75 w load requires an external transistor. the switches configuration is defined by words of 16 bits: one word of 16 bits for each output channel. so, 6 words of 16 bits are necessary to determine the starting configuration upon power-on (power supply: 0 to 10v). but a new configuration needs only the words of the changed output channels. figure 1: tea6415c block diagram 20 11 10 8 6 5 3 1 18 17 16 15 14 13 12 ground output output output output output output input input input input input input input input bus decoder 2749 19 data prog clock vcc ground tea6415c
electrical characteristics tea6415c 3/11 2 electrical characteristics 2.1 absolute maximum ratings 2.2 thermal data 2.3 supply (t a = 25 c , v cc = 10 v , r load = 10 kw , c load = 3 pf (unless otherwise specified) symbol parameter value unit v cc supply voltage (pin 9) 12 v t a operating ambient temperature range 0 to +70 o c t stg storage temperature range -20 to +150 o c symbol parameter value unit r thja junction-to-ambient thermal resistance dip20 so20 80 100 o c/w symbol parameter min. typ. max. unit v cc supply voltage (pin 9) 8 10 11 v i cc power supply current (without load on outputs; v cc = 10 v) 20 30 40 ma inputs signal amplitude (cvbs signal) 2 v pp input current (per output connected, input voltage = 5 v dc ) (this current is multiplied by 6 when all outputs are connected on the input) 13 a dc level 3.3 3.6 3.9 v dc level shift (temperature from 0 to 70c) 5 100 mv outputs (v in = 1 v pp for all dynamic tests) pins 13,14, 15, 16, 17 and 18 dynamic 4.5 5.5 v pp output impedance 25 50 w gain 6 6.5 7 db bandwidth -1db attenuation -3db attenuation 715 20 mhz crosstalk f = 3.58 mhz f = 5 mhz - 55 - 60 - 45 - 50 db dc level 2.4 2.75 3.1 v i 2 c bus input: data, clock and prog (pins 2, 4 and 7) threshold voltage 1.5 2 3 v
4/11 tea6415c electrical characteristics 2.4 i2c bus characteristics symbol parameter test conditions min. max. unit scl v il low level input voltage - 0.3 + 1.5 v v ih high level input voltage 3.0 v cc + 0.5 v i li input leakage current v i = 0 to v cc - 10 + 10 a f scl clock frequency 0 100 khz t r input rise time 1.5 v to 3 v 1000 ns t f input fall time 3 v to 1.5 v 300 ns c i input capacitance 10 pf sda v il low level input voltage - 0.3 + 1.5 v v ih high level input voltage 3.0 v cc + 0.5 v i li input leakage current v i = 0 to v cc - 10 + 10 a c i input capacitance 10 pf t r input rise time 1.5 v to 3 v 1000 ns t f input fall time 3 v to 1.5 v 300 ns v ol low level output voltage i ol = 3ma 0.4 v t f output fall time 3 v to 1.5 v 250 ns c l load capacitance 400 pf timing t low clock low period 4.7 s t high clock high period 4.0 s t su , dat data set-up time 250 ns t hd , dat data hold time 0 340 ns t su , sto set-up time from clock high to stop 4.0 s t buf start set-up time following a stop 4.7 s t hd, sta start hold time 4.0 s t su, sta start set-up time following clock low-to high transition 4.7 s figure 2: i2c bus timing t buf t low t high t hd,sta t r t f t su,sta t hd,dat t su,dat t su,sto sda scl sda
electrical characteristics tea6415c 5/11 2.5 i2c bus selections the i2c chip address is defined by the first byte. the second byte defines the input/output configuration. chip address byte (1st byte of transmission) input/output selection byte (2nd byte of transmission) example : 00100 101 connects pin 10 (input) to pin 14 (output) (equals 25 in hexadecimal) 86 (hex) 1000 0110 (bin) when prog pin is connected to ground 06 (hex) 0000 0110 (bin) when prog pin is connected to v cc table 1: i2c bus output selections output address (msb) input address (lsb) selected output 00000 xxx pin 18 output is selected by the 5 msbs. 00100 xxx pin 14 00010 xxx pin 16 00110 --- not used 00001 xxx pin 17 00101 xxx pin 13 00011 xxx pin 15 00111 --- not used table 2: i2c bus input selections output address (msb) input address (lsb) selected input 00xxx 000 pin 5 input is selected by the 3 lsbs. 00xxx 100 pin 8 00xxx 010 pin 3 00xxx 110 pin 20 00xxx 001 pin 6 00xxx 101 pin 10 00xxx 011 pin 1 00xxx 111 pin 11
6/11 tea6415c electrical characteristics 2.6 input/output pin configuration input configuration figure 3: input configuration figure 4: output configuration v cc 6 times 0.36 v cc pins 1, 3, 5, 6, 8, 10, 11 and 20 v cc all video outputs pins 13, 14, 15, 16, 17 and 18 x 3 8 npn transistors output 7k w 14 k w 11 k w figure 5: bus i/o configuration figure 6: vcc pin configuration pins 2, 4 and 7 20 k w 150 w * * for pin 2 (data) only ack v ref 250 a to i 2l part v cc 9 150 w 20 k w
electrical characteristics tea6415c 7/11 2.7 using a second tea6415c the programming input pin (prog) allows two tea6415c circuits to operate in parallel and to select them independently through the i2c bus by modifying the address byte. consequently, the switching capabilities are doubled, or ic1 and ic2 can be cascaded. figure 7: cascadable tea6415c configuration mcu prog ic1 prog ic2 video outputs video outputs video inputs video inputs logical 1 logical 0
8/11 tea6415c electrical characteristics 2.8 crosstalk improvement 1. whenever an input is not used, it must be bypassed to ground through a 220 nf capacitor. 2. performances can be greatly improved in regards to input crosstalk by using the ap plication example described in the figure below. figure 8: application diagram example 11 12 13 14 15 16 17 18 19 20 1 2 3 6 5 4 9 8 7 10 100 k w 75 w 10 w 75 w 100 k w 75 w 100 k w 75 w 75 w 75 w 220 nf 220 nf 220 nf 220 nf 220 nf 100 f 22 f 220 nf yext v cc (10 v) cvbs 3 prog (bus) cint yint clock (bus) cvbs 2 data (bus) cvbs 1 22 f 75 w 100 k w 10 k w 10 k w 10 k w 10 k w 10 k w 10 k w 220 nf 75 w cext cvbsout2 yout2 cvbsout1 cout2 cout1 yout1 y+c y, c adder y, c separator
package mechanical data tea6415c 9/11 3 package mechanical data figure 9: 20-pin plastic dual in-line package, 300-mil width table 3: dip20 package dim. mm inches min. typ. max. min. typ. max. a 5.33 0.210 a1 0.38 0.015 a2 2.92 3.30 4.95 0.115 0.130 0.195 b 0.36 0.46 0.56 0.014 0.018 0.022 b2 1.14 1.52 1.78 0.045 0.060 0.070 c 0.20 0.25 0.36 0.008 0.010 0.014 d 24.89 26.92 0.980 1.060 e 2.54 0.100 e1 6.10 6.35 7.11 0.240 0.250 0.280 l 2.92 3.30 3.81 0.115 0.130 0.150 number of pins n 20 d e3 sb2 b e a1 a a2 l c e1 e1 g e4 k1 k2
10/11 tea6415c package mechanical data figure 10: 20-pin plastic small outline package, 300-mil width table 4: so20 package dim. mm inches min. typ. max. min. typ. max. a 2.35 2.65 0.0926 0.1043 a1 0.10 0.0040 b 0.33 0.51 0.0130 0.0200 c 0.32 0.0125 d 4.98 13.00 0.1961 0.5118 e 7.40 7.60 0.2914 0.2992 e 1.27 0.050 h 10.01 10.64 0.394 0.419 h 0.25 0.74 0.010 0.029 k 0 8 0 8 l 0.41 1.27 0.016 0.050 g 0.10 0.004 number of pins n 20 e h seating plane g b e a1 a d l k h h c
tea6415c 11/11 notes: information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result f rom its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information pr eviously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems with out express written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics ? 2003 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. www.st.com

▲Up To Search▲

Price & Availability of TEA6415CDT

	To Download TEA6415CDT Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .